データフローアーキテクチャ

Instead of focusing on providing the most possible compute while ignoring memory optimizations like traditional architectures, SambaNova uses Dataflow Architecture to minimize data movement. As one of the most expensive operations in hardware, optimizing data movement enables scaling of large inference deployments in a cost-effective manner.

SambaNova's approach focuses on solving the AI data movement bottleneck directly in hardware, making it faster and more energy-efficient for LLM inference and large-scale AI.

Dataflow is a unique technology that creates an assembly line of operations, which eliminates the memory bottlenecks faced by other solutions. Memory and compute run in parallel on-chip, keeping activations local and reducing data movement.

Instead of operating kernel-by-kernel, a grid of PCUs and SRAM PMUs enables the SambaNova Dataflow Architecture. While compute happens for one operator, data is fetched in parallel for the next to create a streaming pipeline. Parallelization of memory and compute on-chip keeps all intermediate activations local, dramatically reducing unnecessary data movement.