Dataflow 101

How GPUs Process AI

Description:

Explore how GPUs went from rendering graphics to powering AI, how their cores, HBM, and interconnects map to compute, memory, and communication, and why kernel-by-kernel execution sends data on constant round trips to memory.

Additional Resources:

Blog: What is an AI chip

Blog: Why dataflow matters

Product: RDU

How RDUs Process AI

Description

Find out how the Reconfigurable Dataflow Unit (RDU) fuses operations into one continuous pipeline, removing the memory round trips between kernels and reconfiguring itself to match each model's dataflow graph.

Designed for How Data Moves

Description

Discover how RDUs stream data through the chip along the dataflow graph, keeping decode moving and serving more concurrent users without hitting the memory wall that limits GPU-based inference.

Why RDUs have 3 Tier Memory Architectures

Description

Learn how SambaNova Reconfigurable Dataflow Units (RDUs) use a three-tier memory architecture of on-chip SRAM, HBM, and DDR to keep hot data close to compute, reduce unnecessary data movement, and keep inference running efficiently.

Where GPUs Hit Limits

Description:

Learn why GPUs struggle during decode, where the bottleneck shifts from math to memory, and how growing KV caches across concurrent users limit how many people a single GPU can serve.

Additional Resources:

Blog: Why agentic inference needs hybrid hardware

Blog: Hot Chips 2026: Dataflow at scale

Product: RDU

How AI Chips Complement Each Other in Data Centers

Description

Explore why production AI runs on CPUs, GPUs, and RDUs working side by side, and how a heterogeneous data center matches each chip to the workload it was built for.